The present invention generally pertains to charge coupled devices and is particularly directed to an improvement in conserving energy during charge transfer.
A typical prior art charge coupled device (CCD) includes a semiconductor substrate; a source diffusion in the substrate; a drain diffusion in the substrate; an insulating dielectric layer covering the substrate; and a serial array of electrodes defining a serial array of corresponding gates in the dielectric layer extending from the region adjacent the source to the region adjacent the drain, wherein alternate electrodes are transfer electrodes and storage electrodes respectively. Driver circuits are connected to the electrodes to control the transfer of charge packets through the device.
The driver circuits include a plurality of transfer gate driver circuits connected to the transfer electrodes for selectively placing first control signals on their corresponding transfer gates to condition their respective corresponding semiconductor substrate regions for enabling a charge packet to be transferred in the substrate between those regions beneath the gates corresponding to the adjacent storage electrodes when the first control signal placed on the intervening transfer gate is of at least a transfer potential; and a plurality of storage gate driver circuits connected to the storage electrodes for selectively placing second control signals on their corresponding storage gates to condition their respective corresponding semiconductor substrate regions for enabling a charge packet to be stored in selected substrate regions when the second control signal is of at least a storage potential.
A typical prior art four-phase CCD includes four driver circuits.
A first driver circuit is connected to a series of first transfer electrodes consisting of every other transfer electrode beginning with the first transfer electrode in the serial array, for placing a first control signal on their corresponding first transfer gates to condition their corresponding semiconductor substrate regions for enabling charge packets to be transferred in the substrate between those regions beneath the gates corresponding to the adjacent storage electrodes when the first control signal is of at least a transfer potential.
A second driver circuit is connected to a series of first storage electrodes consisting of every other storage electrode beginning with the second electrode in the serial array, for placing a second control signal on their corresponding first storage gates to condition their corresponding semiconductor substrate regions for enabling charge packets to be stored in the substrate regions beneath the first storage gates when the second control signal is of at least a storage potential.
A third driver circuit is connected to a series of second transfer electrodes consisting of every other transfer electrode beginning with the third electrode in the serial array, for placing a third control signal on their corresponding second transfer gates to condition their corresponding semiconductor substrate regions for enabling charge packets to be transferred in the substrate between those regions beneath the gates corresponding to the adjacent storage electrodes when the third control signal is of at least a transfer potential.
Finally, a fourth driver circuit is connected to a series of second storage electrodes consisting of every other storage electrode beginning with the fourth electrode in the serial array, for placing a fourth control signal on their corresponding second storage gates to condition their corresponding semiconductor substrate regions for enabling charge packets to be stored in the substrate regions beneath the second storage gates when the fourth control signal is of at least a storage potential.
Typically charge is injected in the CCD at its source. However, in some CCD's the source and/or the drain are eliminated and charge is generated through other means, such as photoelectrically.
The operation of a prior art CCD in transferring charge is discussed with reference to FIGS. 1A and 1B. FIG. 1A shows the potential wells defined in the semiconductor substrate regions beneath the gates corresponding to the respective transfer electrodes T1, T2 and storage electrodes S1, S2 by the application of control signals to the electrodes during five successive intervals of operation A, B, C, D and E. FIG. 1B shows the potential at the electrodes T1, S1, T2, S2 during the intervals A, B, C, D and E.
During a first interval "A", a control signal .phi.2 at the storage potential V.sub.s is applied to the first storage electrode S1, and control signals .phi.1, .phi.3 and .phi.4 all being at a rest potential "0" are applied to the first and second transfer electrodes T1, T2 and the second storage electrode S2 respectively. A charge packet 10 is stored in the substrate in a potential well 12 in the region beneath the first storage gate G.sub.S1 corresponding to the first storage electrode S1.
During the next interval "B", the control signal .phi.4 is changed to apply a storage potential V.sub.s to the second storage electrode S2, and thereby define a potential well 14 in the substrate region beneath the second storage gate G.sub.S2 corresponding to the second storage electrode S2.
During the next interval "C", the control signal .phi.3 is changed to apply a transfer potential V.sub.T to the second transfer electrode T2, thereby causing a potential well 16 to be defined in the substrate extending from beneath the first storage gate G.sub.S1 to beneath the second storage gate G.sub.S2. As a result, the charge packet begins to transfer from beneath the first storage gate G.sub.S1.
During the following interval "D", the control signal .phi.2 is returned to rest potential, and the charge packet is transferred within the potential well 18 beneath the second transfer gate G.sub.T2 and the second storage gate G.sub.S2.
Finally during the interval "E" the control signal .phi.3 is returned to rest and the charge packet 10 is stored in the potential well 14 beneath the second storage gate G.sub.S2.
The power consumed in transferring the charge packet 10 from the potential well 12 to the potential well 14 is the total of: EQU PWR=[C.sub.S1 (.DELTA.V.sub..phi.2).sup.2 +C.sub.T2 (.DELTA.V.sub..phi.3).sup.2 ].times.f (Equation 1)
wherein f is the frequency of the control signals .phi.1, .phi.2, .phi.3 and .phi.4; C.sub.S1 and C.sub.T2 are the capacitances at the electrodes S1 and T2 respectively, and .DELTA.V.sub..phi.2 and .DELTA.V.sub..phi.3 are the voltage transitions of the control signals .phi.2 and .phi.3 respectively. The capacitances involved are relatively large and therefore the power can be large for high frequency operation.
It is an object of the present invention to provide a charge coupled device which can transfer charge with less energy consumption.